As data-intensive electronic devices and applications proliferate, data rates continue to increase. To facilitate the use of devices such as programmable logic devices in certain data-intensive, real time applications, hierarchical specialized processing blocks, including lower level specialized processing blocks and a message passing communication structure are increasingly being used. A specialized processing block, such as an intellectual property (IP) block, is a block circuitry, that may be separate from the general-purpose programmable logic of a device on which it is implemented, that is at least partially hardwired to perform a specific function. A specialized processing block (e.g., an IP block) that is at a lower hierarchical level, in terms of the device communications structure, than other specialized processing blocks or circuitry may be referred to as a lower level specialized processing block (e.g., a lower level IP block). Lower level specialized processing blocks are best coordinated using software operating on a processor, which communicates to these specialized processing blocks using a message network. For example, a processor may read and write messages using a memory mapped protocol and messages may be transmitted to or from the lower level specialized processing blocks using a streaming packet based protocol. A very efficient interface may be used between the processor and the message network for use in data-intensive, real time applications.
Message passing networks have come into common use. Many existing message passing networks allow processors or processing blocks (e.g., IP cores) to send and receive messages in order to communicate with each other. For example, network on a chip (NoC) designs have been created and used for communication between IP cores in a system on a chip (SoC). There are also multiple existing interface designs, for use between a processor and the message passing network, that are used by the processor to communicate with specialized processing blocks. As an example of such an interface design, PicaRISC, DPX makes use of a FIFO based message passing mechanism. As another example of an interface design, a processor embedded in a programmable device can send messages by writing the messages directly into the network during a bus write cycle. However, these interface designs have drawbacks. In particular, PicaRISC, DPX tends to be inflexible because of the FIFO requirement, and a design involving writing messages directly into the network tends to be inflexible because the messages need to be contiguously grouped.